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169 lines
3.6 KiB
169 lines
3.6 KiB
global start
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extern long_start
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section .text
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bits 32
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start:
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; point the esp register to the top of our stack
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; (the stack grows downwards)
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mov esp, stack_top
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call check_multiboot
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call check_cpuid
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call check_long_mode
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call setup_ptables
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call enable_paging
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; load the 64-bit gdt
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lgdt [gdt64.pointer]
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; jump into the 64-bit boot stub code
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jmp gdt64.code:long_start
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; Checks that we were actually loaded by a Multiboot-compatible system
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check_multiboot:
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cmp eax, 0x36d76289
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jne .no_multiboot
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ret
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.no_multiboot:
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mov al, "m"
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jmp error
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; Checks that we have a CPUID-enabled processor
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check_cpuid:
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; Check if CPUID is supported by attempting to flip the ID bit (bit 21) in
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; the FLAGS register. If we can flip it, CPUID is available.
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; Copy FLAGS in to EAX via stack
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pushfd
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pop eax
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; Copy to ECX as well for comparing later on
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mov ecx, eax
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; Flip the ID bit
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xor eax, 1 << 21
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; Copy EAX to FLAGS via the stack
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push eax
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popfd
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; Copy FLAGS back to EAX (with the flipped bit if CPUID is supported)
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pushfd
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pop eax
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; Restore FLAGS from the old version stored in ECX (i.e. flipping the ID bit
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; back if it was ever flipped).
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push ecx
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popfd
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; Compare EAX and ECX. If they are equal then that means the bit wasn't
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; flipped, and CPUID isn't supported.
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xor eax, ecx
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jz .no_cpuid
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ret
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.no_cpuid:
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mov al, "c"
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jmp error
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; Checks if long mode is supported
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check_long_mode:
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; test if extended processor info in available
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mov eax, 0x80000000 ; implicit argument for cpuid
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cpuid ; get highest supported argument
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cmp eax, 0x80000001 ; it needs to be at least 0x80000001
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jb .no_long_mode ; if it's less, the CPU is too old for long mode
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; use extended info to test if long mode is available
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mov eax, 0x80000001 ; argument for extended processor info
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cpuid ; returns various feature bits in ecx and edx
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test edx, 1 << 29 ; test if the LM-bit is set in the D-register
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jz .no_long_mode ; If it's not set, there is no long mode
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ret
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.no_long_mode:
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mov al, "2"
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jmp error
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setup_ptables:
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; p4[0] -> p3
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mov eax, p3_table
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or eax, 0b11 ; present + writable
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mov [p4_table], eax
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; p3[0] -> p2
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mov eax, p2_table
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or eax, 0b1 ; present + writable
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mov [p3_table], eax
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; map each p2 entry to a 2mib hugepage
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mov ecx, 0
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.map_p2:
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; p2[ecx] -> huge_page{@2MiB*ecx}
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mov eax, 0x200000 ; 2MiB
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mul ecx ; start address
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or eax, 0b10000011 ; present + writable + huge
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mov [p2_table + ecx*8], eax ; map ecx-th entry
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inc ecx ; increase counter
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cmp ecx, 512 ; whole table is mapped if ecx == 512
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jne .map_p2 ; else map the next entry
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ret
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enable_paging:
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; load P4 to cr3 register (cpu uses this to access the P4 table)
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mov eax, p4_table
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mov cr3, eax
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; enable PAE-flag in cr4 (Physical Address Extension)
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; set the long mode bit in the EFER MSR (model specific register)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; enable paging in the cr0 register
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mov eax, cr0
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or eax, 1 << 31
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mov cr0, eax
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ret
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; Print `ERR: ` + error code to screen and then HLTs
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; lovingly ripped off from Phil Oppermann's os.phil-opp.com
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; parameter: error code (ascii) in al
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error:
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mov dword [0xb8000], 0x4f524f45
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mov dword [0xb8004], 0x4f3a4f52
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mov dword [0xb8008], 0x4f204f20
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mov byte [0xb800a], al
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hlt
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;;; Smol stack (64 bytes) just to make stuff work atm
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section .bss
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align 4096
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p4_table:
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resb 4096
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p3_table:
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resb 4096
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p2_table:
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resb 4096
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p1_table:
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resb 4096
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stack_bottom:
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resb 64
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stack_top:
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section .rodata
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gdt64:
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dq 0 ; zero entry
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.code: equ $ - gdt64 ; new
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dq (1<<43) | (1<<44) | (1<<47) | (1<<53) ; code segment
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.pointer:
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dw $ - gdt64 - 1
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dq gdt64
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